xian-en

xian-en

@xianenhor
0
Followers
2
Following
2
Public Repos
0
Private Repos

Language Breakdown

Lines of code distribution across 2 owned repositories

16K Total LOC
Verilog
11,318 lines
71.4%
N/A
SystemVerilog
4,539 lines
28.6%
N/A
I

I-Shaped Developer

I-shaped

Specialist — deep expertise in Verilog

Verilog
SystemVerilog

Collaboration Network

Global Impact visualization

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xian-en
0 active collaborators

Repos

2

PRs

0

Growth

+18%

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Coding Streak

Contribution activity over the past year

1 day
9
Contributions
8
Commits
0
Pull Requests
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Following
2 total
wavefrontshaping

Sébastien M. Popoff

@wavefrontshaping

 shawntsai0312

Hung Shiang Tsai

@shawntsai0312
Synced via GitHub

Top Repositories

verilog-practice
0 0
Verilog
single-port-RAM-RTL-design-testbench-

SystemVerilog RTL and testbench implementation of a single-port RAM with synchronous write and asynchronous read operations

0 0
SystemVerilog

Open Source Impact

Contributions to external projects

0 merged PRs

No external contributions found.